SH7713 Datasheet, PDF (416/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
3
TEH3
0
R/W Delay from RD or WE Negate to Address
2
TEH2
0
R/W Specify the address hold time from RD or WE negate in
1
TEH1
0
R/W ^{the PCMCIA interface.}
0
TEH0
0
R/W ^{0000: 0.5 cycle}
0001: 1.5 cycles
0010: 2.5 cycles
0011: 3.5 cycles
0100: 4.5 cycles
0101: 5.5 cycles
0110: 6.5 cycles
0111: 7.5 cycles
1000: 8.5 cycles
1001: 9.5 cycles
1010: 10.5 cycles
1011: 11.5 cycles
1100: 12.5 cycles
1101: 13.5 cycles
1110: 14.5 cycles
1111: 15.5 cycles
Burst ROM (Clock Synchronous):
• CS0WCR
Bit
31 to
18
Initial
Bit Name Value R/W

All 0 R
17
BW1
0
R/W
16
BW0
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted between
the second or later access cycles in burst access.
00: 0 cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
Rev.1.50 Aug. 30, 2006 Page 376 of 860
REJ09B0288-0150