SH7713 Datasheet, PDF (116/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
• In privileged and privileged DSP modes, all SR bits can be modified.
• In user DSP mode, the SR can be read by the STC instruction.
• In user DSP mode, the LDC instruction can be issued to the SR but only the DSP extension
bits can be modified.
Table 3.2 Operation of SR Bits in Each Processing Mode
Field
Privileged
Mode
MD = 1 &
DSP = 0
User Mode
MD = 0 &
DSP = 0
Privileged
DSP Mode
MD = 1 &
DSP = 1
User DSP
Mode
MD = 0 &
DSP = 1
Access to
DSP-Related
Bit with
Dedicated
Instruction
Initial Value
after Reset
MD
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
1
instruction
RB
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
1
instruction
BL
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
1
instruction
RC
[11:0]
S: OK, L: OK S, L: Invalid
instruction
S: OK, L: OK S: OK, L: OK SETRC
instruction
000000000000
DSP
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
0
instruction
DMY
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: OK
0
instruction
DMX
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: OK
0
instruction
Q
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
x
instruction
M
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
x
instruction
I[3:0]
S: OK, L: OK S, L: Invalid
instruction
S: OK, L: OK S: OK, L: NG
1111
RF[1:0] S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: OK SETRC
x
instruction
instruction
S
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
x
instruction
T
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
x
instruction
[Legend]
S: STC instruction
L: LDC instruction
OK: STC/LDC operation is enabled.
Invalid instruction:
Exception occurs when an invalid instruction is executed.
NG: Previous value is retained. No change.
x: Undefined
Rev.1.50 Aug. 30, 2006 Page 76 of 860
REJ09B0288-0150