SH7713 Datasheet, PDF (635/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
6
TLREP 0
R/W Transmit Left Channel Repeat
This bit setting is valid when the TDRE bit is set to 1.
When this bit is set to 1, settings of bits SITDR15 to
SITDR0 in SITDR are ignored.
0: Transmits data specified in the SITDR bit in SITDR as
right channel data.
1: Repeatedly transmits data specified in the SITDL bit in
SITDR as right channel data
5
—
0
R Reserved
4
—
0
R These bits are always read as 0. The write value should
always be 0.
3
TDRA3 0
R/W Transmit Right Channel Data Assigns
2
TDRA2 0
R/W Specify the position of right-channel data in transmit frame
1
TDRA1 0
R/W ^{as B′0000 to B′1110. Transmit data for the right channel is}
specified in bits SITDR15 to SITDR0 in SITDR.
0
TDRA0 0
R/W _{Note: If the TDRA3 to TDRA0 bits are set to B′1111,}
operation is not guaranteed.
17.3.4 Serial Receive Data Assign Register (SIRDAR)
SIRDAR is used to specify the position of the receive data in a frame. SIRDAR is initialized by a
power-on reset or software reset.
Initial
Bit
Bit Name Value R/W
15
RDLE
0
R/W
14 to 12 —
All 0 R
Description
Receive Left Channel Data Enable
0: Disables left channel data reception
1: Enables left channel data reception
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev.1.50 Aug. 30, 2006 Page 595 of 860
REJ09B0288-0150