SH7713 Datasheet, PDF (539/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 14 Timer Unit (TMU)
Bit Bit Name Initial Value R/W Description
5
UNIE
0
R/W Underflow Interrupt Control
Controls enabling of interrupt generation when the
status flag (UNF) indicating TCNT underflow has been
set to 1.
0: Interrupt due to UNF (TUNI) is disabled
1: Interrupt due to UNF (TUNI) is enabled
4, 3 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2
TPSC2 0
R/W Timer Prescaler 2 to 0
1
TPSC1 0
R/W Select the TCNT count clock.
0
TPSC0 0
R/W 000: Count on Pφ/4
001: Count on Pφ/16
010: Count on Pφ/64
011: Count on Pφ/256
100: Reserved (Setting prohibited)
101: Reserved (Setting prohibited)
110: Reserved (Setting prohibited)
111: Reserved (Setting prohibited)
14.2.3 Timer Constant Registers (TCOR)
The TMU has three timer constant registers (TCOR), one for each channel. The TCOR registers
set the value to be set in TCNT when TCNT underflows.
The TCOR registers are 32-bit readable/writable registers. They are initialized to H'FFFFFFFF by
a power-on reset or manual reset, but are not initialized, and retain their contents, in standby
mode.
14.2.4 Timer Counters (TCNT)
The TMU has three timer counters (TCNT), one for each channel. The timer counters (TCNT)
counts down upon input of a clock. The input clock is selected using the TPSC2 to TPSC0 bits in
the timer control registers (TCR).
Rev.1.50 Aug. 30, 2006 Page 499 of 860
REJ09B0288-0150