SH7713 Datasheet, PDF (670/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Table 17.12 Setting Condition of Transmit/Receive Interrupt Flag
Setting Condition
Transmit interrupt flag TDREQ bit in SISTR is set to 1
Receive interrupt flag RDREQ bit in SISTR is set to 1
Reset Condition
TDREQ bit in SISTR is cleared to 0
Acknowledge from DMAC
RDREQ bit in SISTR is cleared to 0
Acknowledge from DMAC
Processing when Errors Occur: On occurrence of each of the errors indicated as a status in
SISTR, the SIOF performs the following operations.
• Transmit FIFO underrun (TFUDR)
The immediately preceding transmit data is again transmitted.
• Transmit FIFO overrun (TFOVR)
The contents of the transmit FIFO are protected, and the write operation causing the overrun is
ignored.
• Receive FIFO overrun (RFOVR)
Data causing the overrun is discarded and lost.
• Receive FIFO underrun (RFUDR)
The latest read data is output on the bus (undefined value as specification).
• Frame synchronization error (FSERR)
The internal counter is reset according to the FSYN signal in which an error occurs.
17.4.9 Transmission and Reception Timing
Examples of the SIOF serial transmission and reception are shown in figure 17.13 through figure
17.19.
8-bit Monaural Data (1): Synchronous pulse method, falling edge sampling, slot No.0 used for
transmit and receive data, frame length = 8 bits
Rev.1.50 Aug. 30, 2006 Page 630 of 860
REJ09B0288-0150