SH7713 Datasheet, PDF (16/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

9.3.1 Flow of the User Break Operation ........................................................................ 281
9.3.2 Break on Instruction Fetch Cycle ......................................................................... 283
9.3.3 Break on Data Access Cycle................................................................................. 283
9.3.4 Break on X/Y-Memory Bus Cycle ....................................................................... 285
9.3.5 Sequential Break................................................................................................... 285
9.3.6 Value of Saved Program Counter ......................................................................... 286
9.3.7 PC Trace ............................................................................................................... 287
9.3.8 Usage Examples.................................................................................................... 287
9.4 Usage Notes ....................................................................................................................... 292
Section 10 Power-Down Modes........................................................................ 295
10.1 Overview............................................................................................................................ 295
10.1.1 Power-Down Modes ............................................................................................. 295
10.1.2 Reset ..................................................................................................................... 296
10.1.3 Input/Output Pins.................................................................................................. 298
10.2 Register Descriptions......................................................................................................... 298
10.2.1 Standby Control Register (STBCR)...................................................................... 298
10.2.2 Standby Control Register 2 (STBCR2)................................................................. 300
10.2.3 Standby Control Register 3 (STBCR3)................................................................. 301
10.3 Operation ........................................................................................................................... 302
10.3.1 Sleep Mode ........................................................................................................... 302
10.3.2 Software Standby Mode........................................................................................ 303
10.3.3 Module Standby Function..................................................................................... 305
10.3.4 STATUS Pin Change Timings.............................................................................. 306
Section 11 On-Chip Oscillation Circuits........................................................... 311
11.1 Overview............................................................................................................................ 311
11.1.1 Features................................................................................................................. 311
11.2 Overview of CPG............................................................................................................... 313
11.2.1 CPG Block Diagram ............................................................................................. 313
11.2.2 Input/Output Pins.................................................................................................. 315
11.3 Clock Operating Modes ..................................................................................................... 315
11.4 Register Description .......................................................................................................... 320
11.4.1 Frequency Control Register (FRQCR) ................................................................. 320
11.5 Changing Frequency .......................................................................................................... 322
11.5.1 Changing Multiplication Rate............................................................................... 322
11.5.2 Changing Division Ratio ...................................................................................... 322
11.6 Overview of WDT ............................................................................................................. 323
11.6.1 Block Diagram of WDT ....................................................................................... 323
11.7 Register Descriptions of WDT........................................................................................... 324
Rev.1.50 Aug. 30, 2006 Page xvi of xl