SH7713 Datasheet, PDF (631/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
17.3.1 SIOF Mode Register (SIMDR)
SIMDR is a register that sets the SIOF0/1 operating mode. SIMDR is initialized by a power-on
reset or manual reset.
Initial
Bit Bit Name Value
15 TRMD1 0
14 TRMD0 0
13 
0
12 REDG 0
R/W Description
R/W Transfer Mode
R/W Selects transfer mode.
00: Slave mode 1
01: Slave mode 2
10: Master mode 1
11: Master mode 2
Note: For the operation in each mode, see section 17.4.3,
Transfer Data Format.
R
Reserved
This bit is always read as 0. The write value should always
be 0.
R/W Receive Data Sampling Edge
The TXD_SIO signal is transmitted at the opposite edge
where the RXD_SIO signal is sampled (see figure 17.4).
0: RXD_SIO is sampled at the falling edge of SCK_SIO
1: RXD_SIO is sampled at the rising edge of SCK_SIO
Note: This bit is valid in master mode 1 and master mode
2.
Rev.1.50 Aug. 30, 2006 Page 591 of 860
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