SH7713 Datasheet, PDF (645/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Initial
Bit Bit Name Value R/W Description
4
FSERR 0
R/W Frame Synchronization Error
A frame synchronization error occurs when the next frame
synchronization timing appears before the previous data or
control data transfers have been completed. If a frame
synchronization error occurs, the SIOF performs transmission
or reception for slots that can be transferred.
This bit is valid when the TXE or RXE bit in SICTR is 1. When
1 is written to this bit, the contents are cleared. If the issue of
interrupts by this bit is enabled, the SIOF issues an error
interrupt.
0: Indicates that no frame synchronization error occurs
1: Indicates that a frame synchronization error occurs
3
TFOVR 0
R/W Transmit FIFO Overrun
Transmit FIFO overrun means that there has been an attempt
to write to SITDR when the transmit FIFO is full. When a
transmit overrun occurs, written data is ignored.
This bit is valid when the TXE bit in SICTR is 1. When 1 is
written to this bit, the contents are cleared. If the issue of
interrupts by this bit is enabled, the SIOF issues an error
interrupt.
0: No transmit FIFO overrun
1: Transmit FIFO overrun
2
TFUDR 0
R/W Transmit FIFO Underrun
Transmit FIFO underrun means that loading for transmission
has occurred when the transmit FIFO is empty. When a
transmit underrun occurs, the SIOF repeatedly sends the
previous transmit data.
This bit is valid when the TXE bit in SICTR is 1. When 1 is
written to this bit, the contents are cleared. If the issue of
interrupts by this bit is enabled, the SIOF issues an error
interrupt.
0: No transmit FIFO underrun
1: Transmit FIFO underrun
Rev.1.50 Aug. 30, 2006 Page 605 of 860
REJ09B0288-0150