SH7713 Datasheet, PDF (514/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
Transfer requests from the various modules are specified by the MID and RID as shown in table
13.2.
Table 13.2 DMARS Setting
Peripheral
Module
SCIF0
SCIF1
SIOF0
SIOF1
Setting Value for One
Channel (MID + RID)
H'21
H'22
H'29
H'2A
H'51
H'52
H'55
H'56
MID
B'001000
B'001010
B'010100
B'010101
RID
B'01
B'10
B'01
B'10
B'01
B'10
B'01
B'10
Function
Transmit
Receive
Transmit
Receive
Transmit
Receive
Transmit
Receive
13.4 Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority order; when the transfer end conditions are satisfied, it ends the
transfer. Transfers can be requested in three modes: auto request, external request, and on-chip
peripheral module request. In the bus mode, the burst mode or the cycle steal mode can be
selected.
13.4.1 DMA Transfer Flow
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation
register (DMAOR), and DMA extension resource selector (DMARS) are set, the DMAC transfers
data according to the following procedure:
1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0)
2. When a transfer request comes and transfer is enabled, the DMAC transfers 1 transfer unit of
data (depending on the TS0 and TS1 settings). For an auto request, the transfer begins
automatically when the DE bit and DME bit are set to 1. The DMATCR value will be
decremented for each transfer. The actual transfer flows vary by address mode and bus mode.
Rev.1.50 Aug. 30, 2006 Page 474 of 860
REJ09B0288-0150