SH7713 Datasheet, PDF (173/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

39 31
0
Guard
Source 1 or 2
Section 3 DSP Operating Unit
Priority encoder
DSR
GT Z N V DC
Guard
39 31
Cleared to 0
0
Figure 3.19 PDMSB Operation Flow
The definition of the DC bit is selected by the CS0–CS2 (condition selection) bits in DSR. The
DC bit result is
Carry or Borrow Mode: CS[2:0] = 000: The DC bit is always cleared.
Negative Value Mode: CS[2:0] = 001: The DC bit is set when the operation result is a negative
value, and cleared when the operation result is zero or a positive value.
Zero Value Mode: CS[2:0] = 010: The DC bit is set when the operation result is zero; otherwise
it is cleared.
Overflow Mode: CS[2:0] = 011: The DC bit is always cleared.
Signed Greater Than Mode: CS[2:0] = 100: The DC bit is set when the operation result is a
positive value; otherwise it is cleared.
Signed Greater Than or Equal Mode: CS[2:0] = 101: The DC bit is set when the operation
result is zero or a positive value; otherwise it is cleared.
Rev.1.50 Aug. 30, 2006 Page 133 of 860
REJ09B0288-0150