SH7713 Datasheet, PDF (642/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Initial
Bit Bit Name Value R/W Description
7 RFWM2 0
R/W Receive FIFO Watermark
6 RFWM1 0
5 RFWM0 0
R/W A transfer request to the receive FIFO is issued by the RDREQ
R/W ^{bit in SISTR. The receive FIFO is always used as 16 stages of}
FIFO regardless of these bit settings.
000: Issue a transfer request when 1 stage or more of receive
FIFO are valid.
001: Reserved (setting prohibited)
010: Reserved (setting prohibited)
011: Reserved (setting prohibited)
100: Issue a transfer request when 4 or more stages of receive
FIFO are valid.
101: Issue a transfer request when 8 or more stages of receive
FIFO are valid.
110: Issue a transfer request when 12 or more stages of
receive FIFO are valid.
111: Issue a transfer request when 16 stages of receive FIFO
are valid.
4 RFUA4 0
R
Receive FIFO Usable Area
3 RFUA3 0
2 RFUA2 0
R
Indicate the number of words that can be transferred by the
R
CPU or DMAC as B′00000 to B′10000.
1 RFUA1 0
R
0 RFUA0 0
R
Rev.1.50 Aug. 30, 2006 Page 602 of 860
REJ09B0288-0150