SH7713 Datasheet, PDF(175/904 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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SH7713 Datasheet, PDF (175/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Table 3.29 Variation of PDMSB Operation

Mnemonic

PDMSB

Function

MSB detection

Source

Sx

â

Section 3 DSP Operating Unit

Source 2

â

Sy

Destination

Dz

Dz

The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]

bits. See the negative value mode part above. The Z bit always indicates the same state as the DC

bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit

always indicates the same state as the DC bit set in Overflow mode by the CS[2:0] bit. See the

Overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed

greater than mode by the CS[2:0] bits. See the signed greater than mode part above.

3.5.10 Rounding Operation

The DSP unit provides the function that rounds from 32 bits to 16 bits. In case of providing guard-

bit parts, it rounds from 40 bits to 24 bits. When a round instruction is executed, H'00008000 is

added to the source operand data and then, the lower word is cleared. Figure 3.20 shows the

rounding operation flow and figure 3.21 shows the operation definition. Table 3.30 shows the

variation of this type of operation. The correspondence between each operand and registers is the

same as ALU fixed-point operations as shown in table 3.21.

As shown in figure 3.21, the rounding operation uses full-size data for both source and destination

operands. These operations are executed in the DSP stage as shown in figure 3.10. The DSP stage

is the same stage as the MA stage in which memory access is performed.

Every time rounding operation is executed, the DC, N, Z, V, and GT bits in DSR are basically

updated in accordance with the operation result. In case of a conditional operation, they are not

updated, even though the specified condition is true, and the operation is executed. In case of an

unconditional operation, they are always updated with the operation results. The definition of the

DC bit is selected by the CS0âCS2 (condition selection) bits in DSR. The result of these condition

code bits is the same as the ALU-fixed point arithmetic operations.

Rev.1.50 Aug. 30, 2006 Page 135 of 860

REJ09B0288-0150

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