SH7713 Datasheet, PDF (200/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Exception Handling
3. Control is passed to the address stored in the SPC.
The above operations from 1 to 3 are executed in sequence. During these operations, no other
exceptions may be accepted. By changing the SPC and SSR before executing the RTE instruction,
a status different from that in effect before the exception handling can also be specified.
Notes: 1. The MMU registers are modified if an MMU exception occurs.
2. For details on the CPU processing mode in which RTE delay slot instructions are
executed, please refer to section 4.5, Usage Notes.
4.2.2 Exception Vector Addresses
A vector address for general exceptions is determined by adding a vector offset to a vector base
address. The vector offset for general exceptions other than the TLB error exception is
H′00000100. The vector offset for interrupts is H′00000600. The vector base address is loaded
into the vector base register (VBR) using the software. The vector base address should reside in
the P1 or P2 fixed physical address space.
4.2.3 Exception Codes
The exception codes are written to bits 11 to 0 in EXPEVT (for reset or general exceptions) or
INTEVT2 (for interrupt requests) to identify each specific exception event. See section 8, Interrupt
Controller (INTC), for details on the exception codes for interrupt requests. Table 4.1 lists
exception codes for resets and general exceptions.
4.2.4 Exception Request and BL Bit (Multiple Exception Prevention)
The BL bit in SR is set to 1 when a reset or exception is accepted. While the BL bit is set to 1,
acceptance of general exceptions is restricted as described below, making it possible to effectively
prevent multiple exceptions from being accepted.
If the BL bit is set to 1, an interrupt request is not accepted and is retained. The interrupt request is
accepted when the BL bit is cleared to 0. If the CPU is in low power consumption mode, an
interrupt is accepted even if the BL bit is set to 1 and the CPU returns from the low power
consumption mode.
A DMA error is not accepted and is retained if the BL bit is set to 1 and accepted when the BL bit
is cleared to 0. User break requests generated while the BL bit is set are ignored and are not
retained. Accordingly, user breaks are not accepted even if the BL bit is cleared to 0.
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