SH7713 Datasheet, PDF (420/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W
8
BACTV 0
R/W
7 to 5 
All 0 R
4
A3ROW1 0
R/W
3
A3ROW0 0
R/W
2

0
R
1
A3COL1 0
R/W
0
A3COL0 0
R/W
Description
Bank Active Mode
Specifies to access whether in auto-precharge mode
(using READA and WRITA commands) or in bank active
mode (using READ and WRIT commands).
0: Auto-precharge mode (using READA and WRITA
commands)
1: Bank active mode (using READ and WRIT commands)
Note: Bank active mode can be used only in area 3. In this
case, the bus width can be selected as 16 or 32 bits.
When both areas 2 and 3 are set to SDRAM, specify
auto-precharge mode.
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Bits of Row Address for Area 3
Specify the number of bits of the row address for area 3.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (setting prohibited)
Reserved
This bit is always read as 0. The write value should always
be 0.
Number of Bits of Column Address for Area 3
Specify the number of bits of the column address for area
3.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (setting prohibited)
Rev.1.50 Aug. 30, 2006 Page 380 of 860
REJ09B0288-0150