SH7713 Datasheet, PDF (212/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Exception Handling
4.4 Exception Processing while DSP Extension Function is Valid
When the DSP extension function is valid (the DSP bit of SR is set to 1), some exception
processing acceptance conditions or exception processing may be changed.
4.4.1 Illegal Instruction Exception and Slot Illegal Instruction Exception
In the DSP mode, a DSP extension instruction can be executed. If a DSP extension instruction is
executed when the DSP bit of SR is cleared to 0 (in a mode other than the DSP mode), an illegal
instruction exception occurs.
In the DSP mode, STC and LDC instructions for the SR register can be executed even in user
mode. (Note, however, that only the RC[11:0], DMX, DMY, and RF[1:0] bits in the DSP
extension bits can be changed.)
4.4.2 CPU Address Error
In the DSP mode, a part of the space P2 (Uxy area: H′A5000000 to H′A5FFFFFF) can be accessed
in user mode and no CPU address error will occur even if the area is accessed.
4.4.3 Exception in Repeat Control Period
If an exception is requested or an exception is accepted during repeat control, the exception may
not be accepted correctly or a program execution may not be returned correctly from exception
processing that is different from the normal state. These restrictions may occur from repeat
detection instruction to repeat end instruction while the repeat counter is 1 or more. In this section,
this period is called the repeat control period.
The following shows program examples where the number of instructions in the repeat loop are 4
or more, 3, 2, and 1, respectively. In this section, a repeat detection instruction and its instruction
address are described as RptDtct. The first, second, and third instructions following the repeat
detection instruction are described as RptDtct1, RptDtct2, and RptDtct3. In addition, [A], [B],
[C1], and [C2] in the following examples indicate instructions where a restriction occurs. Table
4.2 summarizes the instruction positions and restriction types.
Rev.1.50 Aug. 30, 2006 Page 172 of 860
REJ09B0288-0150