SH7713 Datasheet, PDF (100/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Table 2.8 Logic Operation Instructions
Instruction
Instruction
Code
Operation
Privileged
Mode
Cycles T Bit
AND Rm,Rn
0010nnnnmmmm1001 Rn & Rm → Rn

1

AND #imm,R0
11001001iiiiiiii
R0 & imm → R0

1

AND.B #imm,@(R0, 11001101iiiiiiii
GBR)
(R0+GBR) & imm →
(R0+GBR)

3

NOT Rm,Rn
0110nnnnmmmm0111 ^∼Rm → Rn

1

OR
Rm,Rn
0010nnnnmmmm1011 RnRm → Rn

1

OR
#imm,R0
11001011iiiiiiii
R0imm → R0

1

OR.B
#imm,@(R0, 11001111iiiiiiii
GBR)
(R0+GBR)imm → (R0+GBR) 
3

TAS.B @Rn
0100nnnn00011011 If (Rn) is 0, 1 → T; 1 → MSB of 
(Rn)
4
Test result
TST Rm,Rn
0010nnnnmmmm1000 Rn & Rm; if the result is 0, 1 → 
T
1
Test result
TST #imm,R0
11001000iiiiiiii
R0 & imm; if the result is 0, 1 
→T
1
Test result
TST.B #imm,@(R0, 11001100iiiiiiii
GBR)
(R0 + GBR) & imm; if the result 
is 0, 1 → T
3
Test result
XOR Rm,Rn
0010nnnnmmmm1010 Rn ^ Rm → Rn

1

XOR #imm,R0
11001010iiiiiiii
R0 ^ imm → R0

1

XOR.B #imm,@(R0, 11001110iiiiiiii
GBR)
(R0+GBR) ^ imm → (R0+GBR) 
3

Rev.1.50 Aug. 30, 2006 Page 60 of 860
REJ09B0288-0150