SH7713 Datasheet, PDF (663/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
• Receive FIFO: The number of valid data stages that can be transferred by the CPU or DMAC
are indicated by the RFUA4 to RFUA0 bits in SIFCTR.
The above contents show the number of data which CPU or DMAC can transfer.
17.4.7 Transmission and Reception Procedures
Transmission in Master Mode: Figure 17.9 shows an example of settings and operation for
master mode transmission.
Rev.1.50 Aug. 30, 2006 Page 623 of 860
REJ09B0288-0150