SH7713 Datasheet, PDF (79/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Initial
Bit
Bit Name Value R/W Description
28
BL
1
R/W Block
Specifies whether an exception, interrupt, or user break is
enabled or not.
0: Enables an exception, interrupt, or user break.
1: Disables an exception, interrupt, or user break.
The BL bit is set to 1 in reset or exception handling state.
27 to 
10
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
9
M

R/W M Bit
8
Q

R/W Q Bit
These bits are used by the DIV0S, DIV0U, and DIV1
instructions. These bits can be changed even in user
mode by using the DIV0S, DIV0U, and DIV1 instructions.
These bits are undefined at reset. These bits do not
change in an exception handling state.
7 to 4 I3 to I0
All 1 R/W Interrupt Mask
Indicates the interrupt mask level. These bits do not
change even if an interrupt occurs. At reset, these bits are
initialized to B'1111. These bits are not affected in an
exception handling state.
3, 2 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
S

R/W Saturation Mode
Specifies the saturation mode for multiply instructions or
multiply and accumulate instructions. This bit can be
specified by the SETS and CLRS instructions in user
mode.
At reset, this bit is undefined. This bit is not affected in an
exception handling state.
Rev.1.50 Aug. 30, 2006 Page 39 of 860
REJ09B0288-0150