SH7713 Datasheet, PDF (312/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 User Break Controller
9.2.8 Break Bus Cycle Register B (BBRB)
BBRB is a 16-bit readable/writable register, which specifies (1) X bus or Y bus, (2) L bus cycle or
I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break
conditions of channel B.
Bit
15 to 10
Bit Name

Initial
Value
All 0
9
XYE
0
8
XYS
0
7
CDB1
0
6
CDB0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Selects the X memory bus or Y memory bus as the
channel B break condition. Note that this bit setting is
enabled only when the L bus is selected with the CDB1
and CDB0 bits. Selection between the X memory bus
and Y memory bus is done by the XYS bit.
0: Selects L bus for the channel B break condition
1: Selects X/Y memory bus for the channel B break
condition
R/W Selects the X bus or the Y bus as the bus of the
channel B break condition.
0: Selects the X bus for the channel B break condition
1: Selects the Y bus for the channel B break condition
R/W L Bus Cycle/I Bus Cycle Select B
R/W Select the L bus cycle or I bus cycle as the bus cycle of
the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
Rev.1.50 Aug. 30, 2006 Page 272 of 860
REJ09B0288-0150