SH7713 Datasheet, PDF (537/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 14 Timer Unit (TMU)
14.2 Register Descriptions
The TMU has the following registers. Refer the section 23, List of Registers, for the addresses and
access size for these registers.
• Timer start register (TSTR)
• Timer constant register 0 (TCOR0)
• Timer counter 0 (TCNT0)
• Timer control register 0 (TCR0)
• Timer constant register 1 (TCOR1)
• Timer counter 1 (TCNT1)
• Timer control register 1 (TCR1)
• Timer constant register 2 (TCOR2)
• Timer counter 2 (TCNT2)
• Timer control register 2 (TCR2)
14.2.1 Timer Start Register (TSTR)
The timer start register (TSTR) selects whether to run or halt the timer counters (TCNT) for
channels 0 to 2.
TSTR is an 8-bit readable/writable register. It is initialized to H'00 by a power-on reset or manual
reset. It is initialized in standby mode when the multiplication ratio of PLL circuit 1 (PLL1) is
changed or when the MSTP2 bit in STBCR is set to 1.
Bit Bit Name Initial Value R/W Description
7 to 3 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2 STR2
0
R/W Counter Start 2
Selects whether to run or halt TCNT2.
0: TCNT2 count halted
1: TCNT2 counts
1 STR1
0
R/W Counter Start 1
Selects whether to run or halt TCNT1.
0: TCNT1 count halted
1: TCNT1 counts
Rev.1.50 Aug. 30, 2006 Page 497 of 860
REJ09B0288-0150