SH7713 Datasheet, PDF (543/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 14 Timer Unit (TMU)
14.4 Interrupts
The interrupt source of TMU is underflow interrupt (TUNI).
14.4.1 Status Flag Set Timing
The UNF bit is set to 1 when the TCNT underflows. Figure 14.5 shows the timing.
Pφ
TCNT
Underflow
signal
UNF
TUNI
H'00000000
TCOR value
Figure 14.5 UNF Set Timing
14.4.2 Status Flag Clear Timing
The status flag can be cleared by writing 0 from the CPU. Figure 14.6 shows the timing.
TCR write cycle
T1
T2
T3
Pφ
Peripheral address bus
TCR address
UNF
Figure 14.6 Status Flag Clear Timing
Rev.1.50 Aug. 30, 2006 Page 503 of 860
REJ09B0288-0150