SH7713 Datasheet, PDF (736/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Transmit descriptor
31 30 29 28 27 26
0
TTTTT
TD0 ^{A D F F F}
CL PPE
TFS26 to TFS0
TE1 0
31
16
TD1
TDL
31
0
TD2
TBA
Padding (4/20/52 bytes)*
Transmit buffer
Valid transmit data
Note: * According to the descriptor length set by the DL0 and DL1 bits in EDMR, the padding size is determined as follows:
For 16 bytes: Padding = 4 bytes
For 32 bytes: Padding = 20 bytes
For 64 bytes: Padding = 52 bytes
Figure 19.2 Relationship between Transmit Descriptor and Transmit Buffer
Rev.1.50 Aug. 30, 2006 Page 696 of 860
REJ09B0288-0150