SH7713 Datasheet, PDF (582/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
6
RIE
0
R/W Receive Interrupt Enable
Enables or disables generation of a receive-data-full
interrupt (RXI) request when the RDF flag or DR flag
in SCFSR is set to 1, receive-error interrupt (ERI)
request when the ER flag in SCFSR is set to 1, or
break-interrupt (BRI) request when the BRK flag in
SCFSR or the ORER flag in SCLSR is set to 1.
0: Receive-data-full interrupt (RXI) request, receive-
error interrupt (ERI) request, and break-interrupt
(BRI) request disabled*
1: Receive-data-full interrupt (RXI) request, receive-
error interrupt (ERI) request, and break-interrupt
(BRI) request enabled
Note: *
An RXI request can be cleared by reading 1
from the RDF flag or DR flag, then clearing
the flag to 0, or by clearing the RIE bit to 0.
The ERI and BRI requests can be cleared
by reading 1 from the ER, BRK, or ORER
flag, then clearing the flag to 0, or clearing
the RIE and REIE bits to 0.
5
TE
0
R/W Transmit Enable
Enables or disables the start of serial transmission by
the SCIF.
0: Transmission disabled
1: Transmission enabled*
Note: *
SCSMR and SCFCR settings must be
made, the transmit format decided, and the
transmit FIFO reset, before the TE bit is set
to 1.
Rev.1.50 Aug. 30, 2006 Page 542 of 860
REJ09B0288-0150