SH7713 Datasheet, PDF (126/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Execution of a repeat detection instruction must be completed without any branch so that the
CPU can recognize the repeat loop. Therefore, when the execution branches to an instruction
following the repeat detection instruction, the control will not be passed to a repeat start
instruction after executing a repeat end instruction because the repeat loop is not recognized by
the CPU. In this case, the RC[11:0] bits of the SR register will not be changed.
 If a conditional branch instruction is used in the repeat loop, an instruction before a repeat
detection instruction must be specified as a branch destination.
 If a subroutine call is used in the repeat loop, a delayed slot instruction of the subroutine
call instruction must be placed before a repeat detection instruction.
Here, a branch includes a return from an exception processing routine. If an exception whose
return address is placed in an instruction following the repeat detection instruction occurs, the
repeat control cannot be returned correctly. Accordingly, an exception acceptance is restricted
from the repeat detection instruction to the repeat end instruction. Exceptions such as interrupts
that can be retained by the CPU are retained. For exceptions that cannot be retained by the CPU, a
transition to an exception occurs but a program cannot be returned to the previous execution state
correctly. For details, refer to section 4, Exception Handling.
Notes: 1. If a TRAPA instruction is used as a repeat detection instruction, an instruction
following the repeat detection instruction is regarded as a return address. In this case, a
control cannot be returned to the repeat control correctly. In a TRAPA instruction, an
address of an instruction following the repeat detection address is regarded as return
address. Accordingly, to return to the repeat control correctly, place a return address
prior to the repeat detection instruction.
2. If a SLEEP instruction is placed following a repeat detection instruction, a transition to
the low-power consumption state or an exception acceptance such as interrupts can be
performed correctly. In this case, however, the repeat control cannot be returned
correctly. To return to the repeat control correctly, the SLEEP instruction must be
placed prior to the repeat detection instruction.
5. Branch from a repeat detection instruction
If a repeat detection instruction is a delayed slot instruction of a delayed branch instruction or a
branch instruction, a repeat loop can be acknowledged when a branch does not occur in a
branch instruction. If a branch occurs in a branch instruction, a repeat control is not performed
and a branch destination instruction is executed.
6. Program counter during repeat control
Rev.1.50 Aug. 30, 2006 Page 86 of 860
REJ09B0288-0150