SH7713 Datasheet, PDF (713/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name Value R/W Description
31 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
TR
0
R/W Transmit Request
0: Transmission-halted state. Writing 0 does not stop
transmission. Termination of transmission is
controlled by the TACT bit of the transmit
descriptor.
1: Transmit DMA operation being performed by the E-
DMAC. After writing 1 to this bit, the E-DMAC
starts reading a transmit descriptor.
19.2.3 E-DMAC Receive Request Register (EDRRR)
EDRRR is a 32-bit readable/writable register that issues receive directives to the E-DMAC. After
writing 1 to the RR bit in this register, the E-DMAC reads the receive descriptor at the address
specified by RDLAR. If the RACT bit of this descriptor is set to 1 (valid), and the receive FIFO
holds a receive frame, the E-DMAC starts receive DMA transfer. When DMA transfer based on
the first receive descriptor is completed, the E-DMAC reads the next receive descriptor. If the
RACT bit of that descriptor is set to 1 (valid), the E-DMAC continues receive DMA operation.
However, if the receive FIFO holds no receive data, the E-DMAC places receive DMA operation
in the standby state. If the RACT bit of the receive descriptor is cleared to 0 (invalid), the E-
DMAC clears the RR bit and stops receive DMAC operation.
For details of writing to the RR bit, see section 19.4.1, Using of EDTRR and EDRRR.
Rev.1.50 Aug. 30, 2006 Page 673 of 860
REJ09B0288-0150