SH7713 Datasheet, PDF (608/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Serial Data Reception: Figures 16.6 and 16.7 show a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
Start of reception
Read ER, DR, and BRK flags in
SCFSR and ORER flag in SCLSR
ER, DR, BRK,
or ORER = 1?
No
Yes
Error handling
Read RDF flag in SCFSR
No
RDF = 1?
Yes
Read receive data from
SCFRDR, and clear RDF flag
in SCFSR to 0
No
All data received?
Yes
Clear RE bit in SCSCR to 0
1. Receive error handling and break detection:
Read the DR, ER, and BRK flags in SCFSR
and ORER flag in SCLSR to identify any
error, perform the appropriate error
handling, then clear the DR, ER, BRK, and
ORER flags to 0. In the case of a framing
error, a break can also be detected by
reading the value of the RxD pin.
2. SCIF status check and receive data read:
Read SCFSR and check that RDF = 1, then
read the receive data in SCFRDR, read 1
from the RDF flag, and then clear the RDF
flag to 0. The transition of the RDF flag
from 0 to 1 can also be identified by an RXI
interrupt.
3. Serial reception continuation procedure:
To continue serial reception, read at least
the receive trigger set number of data bytes
from SCFRDR, read 1 from the RDF flag,
and then clear the RDF flag to 0. The
number of receive data bytes in SCFRDR
can be ascertained by reading the lower
bits of SCFDR.
End of reception
Figure 16.6 Sample Serial Reception Flowchart (1)
Rev.1.50 Aug. 30, 2006 Page 568 of 860
REJ09B0288-0150