SH7713 Datasheet, PDF (268/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 6 Cache
(1) Address array access
(a) Address specification
Read access
31
24
1111 0000
23
14
*--------*
13 12
W
11
4
Entry address
Write access
31
24
1111 0000
23
14
*--------*
13 12
W
11
4
Entry address
3
2
0
0
*00
3
2
0
A
*00
(b) Data specification (both read and write accesses)
31
Tag address (31 to 10)
10 9
4
LRU
3
2
XX
1
0
UV
(2) Data array access (both read and write accesses)
(a) Address specification
31
24 23
14 13 12
1111 0001
*--------*
W
11
4
Entry address
(b) Data specification
31
Longword
3
21
0
L
00
0
*: Don’t care bit
X: 0 for read, don’t care for write
Figure 6.4 Specifying Address and Data for Memory-Mapped Cache Access
(16 kbytes mode)
Rev.1.50 Aug. 30, 2006 Page 228 of 860
REJ09B0288-0150