SH7713 Datasheet, PDF (715/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.2.5 Receive Descriptor List Address Register (RDLAR)
RDLAR is a 32-bit readable/writable register that specifies the start address of the receive
descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length
indicated by the DL bit in EDMR. This register must not be written to during reception.
Modifications to this register should only be made while reception is disabled by the RR bit (= 0)
in the E-DMAC Receive Request Register (EDRRR).
Initial
Bit
Bit Name Value R/W Description
31 to 0 RDLA31 to All 0
RDLA0
R/W Receive Descriptor Start Address
The lower bits are set as follows according to the
specified descriptor length.
16-byte boundary: RDLA3 and RDLA0 = 0000
32-byte boundary: RDLA4 and RDLA0 = 00000
64-byte boundary: RDLA5 and RDLA0 = 000000
19.2.6 EtherC/E-DMAC Status Register (EESR)
EESR is a 32-bit readable/writable register that shows communications status information on the
E-DMAC in combination with the EtherC. The information in this register is reported in the form
of interrupt sources. Individual bits are cleared by writing 1 (however, bit 22 (ECI) is a read-only
bit and not to be cleared by writing 1) and are not affected by writing 0. Each interrupt source can
also be masked by means of the corresponding bit in the EtherC/E-DMAC status interrupt
permission register (EESIPR).
The interrupt generated by this register is EINT0. For interrupt priorities, see section 8, Interrupt
Controller (INTC) and section 8.3.5, Interrupt Exception Handling and Priority.
Initial
Bit
Bit Name Value R/W Description
31

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev.1.50 Aug. 30, 2006 Page 675 of 860
REJ09B0288-0150