SH7713 Datasheet, PDF (353/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 11 On-Chip Oscillation Circuits
11.2 Overview of CPG
11.2.1 CPG Block Diagram
A block diagram of the on-chip clock pulse generator is shown in figure 11.1.
CKIO
CKIO2
XTAL
EXTAL
Clock pulse generator
PLL circuit 1
( 1, 2, 3)
Divider 1
1
1/2
1/3
1/4
1/6
Internal clock
(I )
Crystal
oscillator
PLL circuit 2
( 1, 2, 4)
CPG control unit
Clock frequency
control circuit
FRQCR
Bus clock
(B =CKIO)
Peripheral clock
(P )
Standby control
circuit
STBCR STBCR2 STBCR3
Bus interface
Internal bus
[Legend]
FRQCR: Frequency control register
STBCR: Standby control register
STBCR2: Standby control register 2
STBCR3: Standby control register 3
Figure 11.1 Block Diagram of CPG
Rev.1.50 Aug. 30, 2006 Page 313 of 860
REJ09B0288-0150