SH7713 Datasheet, PDF (692/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.17 Too-Long Frame Receive Counter Register (TLFRCR)
TLFRCR is a 32-bit counter that indicates the number of frames received with a length exceeding
the value specified by the receive frame length register (RFLR). When the value in this register
reaches H'FFFFFFFF, the count is halted. TLFRCR is not incremented when a frame containing
residual bits is received. In this case, the reception of the frame is indicated in the residual-bit
frame counter register (RFCR). The counter value is cleared to 0 by a write to this register with
any value.
Initial
Bit
Bit Name Value
31 to 0 TLFC31 to All 0
TLFC0
R/W
R/W
Description
Too-Long Frame Receive Count
These bits indicate the count of frames received with a
length exceeding the value in RFLR.
18.3.18 Residual-Bit Frame Receive Counter Register (RFCR)
RFCR is a 32-bit counter that indicates the number of frames received containing residual bits
(less than an 8-bit unit). When the value in this register reaches H'FFFFFFFF, the count is halted.
The counter value is cleared to 0 by a write to this register with any value.
Initial
Bit
Bit Name Value R/W
Description
31 to 0 RFC31 to All 0
RFC0
R/W Residual-Bit Frame Receive Count
These bits indicate the count of frames received
containing residual bits.
Rev.1.50 Aug. 30, 2006 Page 652 of 860
REJ09B0288-0150