SH7713 Datasheet, PDF (366/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 11 On-Chip Oscillation Circuits
Initial
Bit
Bit Name Value R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Description
Clock Select 2 to 0
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock. The overflow period in the table is
the value when the peripheral clock (Pφ) is 15 MHz.
Clock
Select
000
001
010
011
100
101
110
111
Clock
Division Ratio
1
1/4
1/16
1/32
1/64
1/256
1/1024
1/4096
Overflow Period
(when P =15MHz)
17 s
68 s
273 s
546 s
1.09 ms
4.36 ms
17.48 ms
69.91 ms
Note:
If bits CKS2 to CKS0 are modified when the
WDT is running, the up-count may not be
performed correctly. Ensure that these bits
are modified only when the WDT is not
running.
11.7.3 Notes on Register Access
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are
more difficult to write to than other registers. The procedure for writing to these registers are given
below.
Writing to WTCNT and WTCSR: These registers must be written by a word transfer
instruction. They cannot be written by a byte or longword transfer instruction.
When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data,
as shown in figure 11.3. When writing to WTCSR, set the upper byte to H'A5 and transfer the
lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or
WTCSR.
Rev.1.50 Aug. 30, 2006 Page 326 of 860
REJ09B0288-0150