SH7713 Datasheet, PDF (129/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
• Example 1: Repeat loop consisting of 4 or more instructions
LDRS RptStart
; Sets repeat start instruction address
to the RS register
LDRE RptEnd
; Sets repeat end instruction address
to the RE register
LDRC #4
; Sets the number of repetitions (4) to
the RC[11:0] bits of the SR register
instr0
; At least one instruction is required
from LDRC instruction to [Repeat start
instruction]
RptStart: instr1
; [Repeat start instruction]
... ...
;
... ...
;
instr(N-3)
;
instr(N-2)
;
instr(N-1)
;
RptEnd: instrN
; [Repeat end instruction]
• Example 2: Repeat loop consisting of three instructions
LDRS RptStart
; Sets repeat start instruction address
to the RS register
LDRE RptEnd
; Sets repeat end instruction address
to the RE register
LDRC #4
; Sets the number of repetitions (4) to
the RC[11:0] bits of the SR register
instr0
; At least one instruction is required
from LDRC instruction to [Repeat start
instruction]
RptStart: instr1
; [Repeat start instruction]
instr2
;
RptEnd: instr3
; [Repeat end instruction]
Rev.1.50 Aug. 30, 2006 Page 89 of 860
REJ09B0288-0150