SH7713 Datasheet, PDF (112/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
instruction fields consist of two fields: field A and field B. In field A, a function for double data
transfer instructions can be descried. In field B, ALU operation instructions and multiply
instructions can be described. The instructions described in fields A and B can be executed in
parallel. A maximum of four instructions (ALU operation, multiply, and two data transfers) can be
executed in parallel. For details, refer to section 3.5, DSP Data Operation Instructions.
Notes: 1. 32-bit instruction codes are handled as two consecutive 16-bit instruction codes.
Accordingly, 32-bit instruction codes can be assigned to a word boundary. 32-bit
instruction codes must be stored in memory, upper word and lower word, in this order,
in word units.
2. In little endian, the upper and lower words must be stored in memory as data to be
accessed in word units.
CPU core instruction
15
12 11
0
0000
*
1110
15
10 9
0
Double-data transfer instruction
111100
A Field
15
10 9
0
Single-data transfer instruction
111101
A Field
31
26 25
16 15
0
DSP data operation instruction
111110
A Field
B Field
Figure 3.1 DSP Instruction Format
Rev.1.50 Aug. 30, 2006 Page 72 of 860
REJ09B0288-0150