SH7713 Datasheet, PDF (399/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Bit
5 to 2
Initial
Bit Name Value R/W

All 0 R
1
HW1
0
R/W
0
HW0
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from RD, WEn (BEn) negation to
Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS5BWCR
Bit
31 to
21
20
19
Initial
Bit Name Value R/W

All 0 R
BAS
0
R/W

0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
and asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn (BEn) signal during the read/write
access cycle and asserts the RD/WR signal at the write
timing.
Reserved
This bit is always read as 0. The write value should always
be 0.
Rev.1.50 Aug. 30, 2006 Page 359 of 860
REJ09B0288-0150