SH7713 Datasheet, PDF (201/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Exception Handling
If a general exception other than a DMA address error or user break occurs while the BL bit is set
to 1, the CPU enters a state similar to that in effect immediately after a reset, and passes control to
the reset vector (H′A0000000) (multiple exception). In this case, unlike a normal reset, modules
other than the CPU are not initialized, the contents of EXPEVT, SPC, and SSR are undefined, and
this status is not detected by an external device.
To enable acceptance of multiple exceptions, the contents of SPC and SSR must be saved while
the BL bit is set to 1 after an exception has been accepted, and then the BL bit must be cleared to
0. Before restoring the SPC and SSR, the BL bit must be set to 1.
4.2.5 Exception Source Acceptance Timing and Priority
Exception Request of Instruction Synchronous Type and Instruction Asynchronous Type:
Resets and interrupts are requested asynchronously regardless of the program flow. In general
exceptions, a DMA address error and a user break under the specific condition are also requested
asynchronously. The user cannot expect on which instruction an exception is requested. For
general exceptions other than a DMA address error and a user break under a specific condition,
each general exception corresponds to a specific instruction.
Re-Execution Type and Processing-Completion Type Exceptions: All exceptions are classified
into two types: a re-execution type and a processing-completion type. If a re-execution type
exception is accepted, the current instruction executed when the exception is accepted is
terminated and the instruction address is saved to the SPC. After returning from the exception
processing, program execution resumes from the instruction where the exception was accepted. In
a processing-completion type exception, the current instruction executed when the exception is
accepted is completed, the next instruction address is saved to the SPC, and then the exception
processing is executed.
During a delayed branch instruction and delay slot, the following operations are executed. A re-
execution type exception detected in a delay slot is accepted before executing the delayed branch
instruction. A processing-completion type exception detected in a delayed branch instruction or a
delay slot is accepted when the delayed branch instruction has been executed. In this case, the
acceptance of delayed branch instruction or a delay slot precedes the execution of the branch
destination instruction. In the above description, a delay slot indicates an instruction following an
unconditional delayed branch instruction or an instruction following a conditional delayed branch
instruction whose branch condition is satisfied. If a branch does not occur in a conditional delayed
branch, the normal processing is executed.
Rev.1.50 Aug. 30, 2006 Page 161 of 860
REJ09B0288-0150