SH7713 Datasheet, PDF (278/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
8.3.2 IRQ Interrupts
IRQ interrupts are input by level or edge from pins IRQ0 to IRQ5. The priority level can be set by
interrupt priority registers C and D (IPRC and IPRD) in a range from 0 to 15.
When using edge-sensing for IRQ interrupts, clear the interrupt source by having software read 1
from the corresponding bit in IRR0, then write 0 to the bit.
When ICR1 is rewritten, IRQ interrupts may be mistakenly detected, depending on the IRQ pin
states. To prevent this, rewrite the register while interrupts are masked, then release the mask after
clearing the illegal interrupt by writing 0 to interrupt request register 0 (IRR0).
Edge input interrupt detection requires input of a pulse width of more than two cycles on a P clock
basis.
When using level-sensing for IRQ interrupts, the pin levels must be retained until the CPU
samples the pins. Therefore, the interrupt source must be cleared by the interrupt handler.
The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRQ interrupt
handling. IRQ interrupts can be used for recovering from standby when the corresponding
interrupt level is higher than that of bits I3 to I0 in SR. (However, only when the RTC is used,
recovering from standby by using the clock for the RTC is enabled.)
8.3.3 IRL Interrupts
IRL interrupts are input by the IRL3 to IRL0 pins as level. The priority level is the higher level
that is indicated by the IRL3 to IRL0 pins. When the values of the IRL3 to IRL0 pins are 0
(B′0000), the highest level interrupt request (interrupt priority level 15) is indicated. When the
values of the pins are 15 (B′1111), no interrupt is requested (interrupt priority level 0). Figure 8.2
shows an example of connection for an IRL interrupt. Table 8.3 lists the IRL pins and interrupt
level.
IRL interrupts are included with a noise canceler function and detected when the sampled levels of
each peripheral module clock keep the same value for 2 cycles. This prevents sampling error level
in IRL pin changing. In standby mode, a noise canceler is handled by the RTC clock (32 kHz)
because the peripheral module clocks are halted. Therefore, when the RTC is not used, recovering
from standby by IRL interrupts cannot be executed in standby mode.
The priority level of IRL interrupts should be kept until an interrupt is accepted and its handling is
started. However, changing to higher level is enabled.
Rev.1.50 Aug. 30, 2006 Page 238 of 860
REJ09B0288-0150