SH7713 Datasheet, PDF (519/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
register. Likewise, when a transfer request is set to RXI of the SCIF0, the transfer source must be
the SCIF0's receive data register. These conditions also apply to the SCIF1, SIOF0, and SIOF1.
Depending on the on-chip peripheral module, the number of receive FIFO triggers can be set as a
transfer request. If the receive FIFO trigger condition is not satisfied, data may be remained in the
receive FIFO. Therefore, data needs to be read upon completion of the DMA transfer.
Table 13.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
CHCR
RS[3:0]
1000
DMARS
MID
RID
001000 01
10
001010 01
10
010100 01
10
010101 01
10
DMA Transfer
Request
DMA Transfer
Source
Request Signal
SCIF0
transmitter
TXI (transmit FIFO data
empty interrupt)
SCIF0
receiver
RXI (receive FIFO data
full interrupt)
SCIF1
transmitter
TXI (transmit FIFO data
empty interrupt)
SCIF1
receiver
RXI (receive FIFO data
full interrupt)
SIOF0
transmitter
TXI (transmit FIFO data
empty interrupt)
SIOF0
receiver
RXI (receive FIFO data
full interrupt)
SIOF1
transmitter
TXI (transmit FIFO data
empty interrupt)
SIOF1
receiver
RXI (receive FIFO data
full interrupt)
Source
Any
SCFRDR_0
Any
SCFRDR_1
Any
SIOF0/
SIRDR_0
Any
SIOF1/
SIRDR_1
Destination
SCFTDR_0
Any
SCFTDR_1
Any
SITDR_0
Any
SITDR_1
Any
Bus
Mode
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
13.4.3 Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it selects a
channel according to a predetermined priority order. The two modes (fixed mode and round-robin
mode) can be selected using bits PR0 and PR1 in DMAOR.
Fixed Mode: In this mode, the priority levels among the channels remain fixed. There are two
kinds of fixed modes as follows:
Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5
Fixed mode 2: CH0 > CH2 > CH3 > CH1 > CH4 > CH5
These are selected by the PR1 and the PR0 bits in DMAOR.
Rev.1.50 Aug. 30, 2006 Page 479 of 860
REJ09B0288-0150