SH7713 Datasheet, PDF (88/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Addressing
Mode
PC-relative
Instruction
Format
Effective Address Calculation Method
Rn
Effective address is sum of PC and Rn.
PC
Calculation
Formula
PC + Rn
+
PC + Rn
Rn
Immediate
#imm:8
8-bit immediate data imm of TST, AND,
—
OR, or XOR instruction is zero-extended.
#imm:8
8-bit immediate data imm of MOV, ADD, or —
CMP/EQ instruction is sign-extended.
#imm:8
8-bit immediate data imm of TRAPA
—
instruction is zero-extended and multiplied
by 4.
Note:
For addressing modes with displacement (disp) as shown below, the assembler description
in this manual indicates the value before it is scaled (x 1, x2, or x4) according to the
operand size to clarify the LSI operation. For details on assembler description, refer to the
description rules in each assembler.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, GBR)
; GBR indirect with displacement
@ (disp:8, PC) ; PC relative with displacement
disp:8, disp ; PC relative
2.5.3 CPU Instruction Formats
Table 2.4 shows the instruction formats, and the meaning of the source and destination operands,
for instructions executed by the CPU core. The meaning of the operands depends on the
instruction code. The following symbols are used in the table.
xxxx: Instruction code
mmmm:
Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement
Rev.1.50 Aug. 30, 2006 Page 48 of 860
REJ09B0288-0150