SH7713 Datasheet, PDF (669/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Table 17.11 SIOF Interrupt Sources
No. Classification Bit Name
1 Transmission TDREQ
(TXI)
2 Reception (RXI) RDREQ
3 Control (CCI) TCRDY
4
RCRDY
5
6
7 Error (ERI)
TFEMP
RFFUL
TFUDR
8
TFOVR
9
RFOVR
10
RFUDR
11
FSERR
Function name
Description
Transmit data transfer The number of transmit FIFO data
request
is equal to or less than the specified
value by transmit operation.
Receive data transfer The receive FIFO stores data of
request
specified value or more.
Transmit control data The transmit control data register is
ready
ready to be written.
Receive control data The receive control data register
ready
stores valid data.
Transmit FIFO empty The transmit FIFO is empty.
Receive FIFO full The receive FIFO is full.
Transmit FIFO
underrun
Serial data transmission timing has
arrived while the transmit FIFO is
empty.
Transmit FIFO
overrun
Write to the transmit FIFO is
performed while the transmit FIFO
is full.
Receive FIFO
overrun
Serial data is received while the
receive FIFO is full.
Receive FIFO
underrun
The receive FIFO is read while the
receive FIFO is empty.
Frame
A synchronous signal is input
synchronization error before the specified bit time has
been passed (in slave mode).
Whether an interrupt is issued or not as the result of an interrupt source is determined by the
SIIER settings. If an interrupt source is set to 1, and the corresponding bit in SIIER is set to 1, the
SIOF issues each interrupt.
Transmit/Receive Interrupt Flag: Transmit and receive interrupts are sent to the INTC or
DMAC by this interrupt flag based on the values of bits TDREQ and RDREQ in SISTR.
Table17.12 shows the setting condition of the transmit/receive interrupt flag.
Rev.1.50 Aug. 30, 2006 Page 629 of 860
REJ09B0288-0150