SH7713 Datasheet, PDF (275/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
Section 8 Interrupt Controller (INTC)
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to process interrupt requests according to the user-set priority.
8.1 Features
The INTC has the following features:
• 16 levels of interrupt priority can be set
By setting the interrupt-priority registers, the priorities of on-chip peripheral modules, and IRQ
interrupts can be selected from 16 levels for individual request sources.
• NMI noise canceler function
An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt
exception service routine, the pin state can be checked, enabling it to be used as a noise
canceler.
• IRQ interrupts can be set
Detection of low level, rising edge, falling edge, or high level
• Interrupt request signal can be externally output (IRQOUT pin)
The bus mastership can be requested by notifying the external bus master that the external
interrupt and on-chip peripheral module interrupt requests have been generated.
8.1.1 Block Diagram
Figure 8.1 shows a block diagram of the INTC.
Rev.1.50 Aug. 30, 2006 Page 235 of 860
REJ09B0288-0150