SH7713 Datasheet, PDF (424/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
12.5 Operation
12.5.1 Endian/Access Size and Data Alignment
This LSI supports big endian, in which the 0 address is the most significant byte (MSByte) in the
byte data and little endian, in which the 0 address is the least significant byte (LSByte) in the byte
data. Endian is specified on power-on reset by the external pin (MD5). When MD5 pin is low
level on power-on reset, the endian will become big endian and when MD5 pin is high level on
power-on reset, the endian will become little endian.
Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and byte-
selection SRAM. Two data bus widths (16 bits and 32 bits) are available for SDRAM. Two data
bus widths (8 bits and 16 bits) are available for PCMCIA interface. Data alignment is performed
in accordance with the data bus width of the device and endian. This also means that when
longword data is read from a byte-width device, the read operation must be done four times. In
this LSI, data alignment and conversion of data length is performed automatically between the
respective interfaces.
Tables 12.6 to 12.11 show the relationship between endian, device data width, and access unit.
Table 12.6 32-Bit External Device/Big Endian Access and Data Alignment
Data Bus
Strobe Signals
Operation
D31 to
D24
D23 to
D16
D15 to
WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0),
D8
D7 to D0 DQMUU DQMUL DQMLU DQMLL
Byte access Data 


Assert 


at 0
7 to 0
Byte access 
Data 


Assert 

at 1
7 to 0
Byte access 

Data 


Assert 
at 2
7 to 0
Byte access 


Data 


Assert
at 3
7 to 0
Word
Data Data 

Assert Assert 

access at 0 15 to 8 7 to 0
Word


Data Data 

Assert Assert
access at 2
15 to 8 7 to 0
Longword Data Data Data Data Assert
access at 0 31 to 24 23 to 16 15 to 8 7 to 0
Assert
Assert
Assert
Rev.1.50 Aug. 30, 2006 Page 384 of 860
REJ09B0288-0150