SH7713 Datasheet, PDF (31/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Figure 18.4 (5) MII Frame Receive Timing (Reception Error (1))............................................. 661
Figure 18.4 (6) MII Fame Receive Timing (Reception Error (2)) .............................................. 661
Figure 18.5 MII Management Frame Format ............................................................................. 662
Figure 18.6 (1) 1-Bit Data Write Flowchart ............................................................................... 663
Figure 18.6 (2) Bus Release Flowchart (TA in Read in Figure 18.5) ......................................... 664
Figure 18.6 (3) 1-Bit Data Read Flowchart ................................................................................ 664
Figure 18.6 (4) Independent Bus Release Flowchart (IDLE in Write in Figure 18.5)................ 665
Figure 18.7 Changing IPG and Transmission Efficiency ........................................................... 666
Figure 18.8 Example of Connection to DP83848 ....................................................................... 667
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Figure 19.1 Configuration of E-DMAC, and Descriptors and Buffers....................................... 670
Figure 19.2 Relationship between Transmit Descriptor and Transmit Buffer ............................ 696
Figure 19.3 Relationship between Receive Descriptor and Receive Buffer ............................... 702
Figure 19.4 Sample Transmission Flowchart (Single-Frame/Two-Descriptor) ................................ 709
Figure 19.5 Sample Reception Flowchart (Single-Frame/Two-Descriptor) ............................... 711
Figure 19.6 E-DMAC Operation after Transmit Error ............................................................... 712
Figure 19.7 E-DMAC Operation after Receive Error................................................................. 713
Figure 19.8 Configuration of ARBUSY ..................................................................................... 714
Figure 19.9 Summary of Receive FIFO Overflow Alert Signal ................................................. 715
Figure 19.10 ARBUSY Signal Change and Minimum Pulse Width Depending on
Increase and Decrease of FIFO ............................................................................. 716
Section 22 User Debugging Interface (H-UDI)
Figure 22.1 Block Diagram of H-UDI........................................................................................ 731
Figure 22.2 TAP Controller State Transitions ............................................................................ 742
Figure 22.3 H-UDI Data Transfer Timing.................................................................................. 744
Figure 22.4 H-UDI Reset............................................................................................................ 744
Section 24 Electrical Characteristics
Figure 24.1 Power On/Off Sequence .......................................................................................... 784
Figure 24.2 EXTAL Clock Input Timing ................................................................................... 789
Figure 24.3 CKIO Clock Input Timing....................................................................................... 789
Figure 24.4 CKIO Clock Output Timing.................................................................................... 790
Figure 24.5 Power-On Oscillation Settling Time ....................................................................... 790
Figure 24.6 Oscillation Settling Time at Standby Return (Return by Reset).............................. 790
Figure 24.7 Oscillation Settling Time at Standby Return (Return by NMI)............................... 791
Figure 24.8 Oscillation Settling Time at Standby Return (Return by IRQ5 to IRQ0 and
IRL3 to IRL0) ......................................................................................................... 791
Figure 24.9 PLL Synchronization Settling Time by Reset or NMI ............................................ 791
Figure 24.10 PLL Synchronization Settling Time by IRQ/IRL Interrupts ................................. 792
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