SH7713 Datasheet, PDF (576/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.1 Receive Shift Register (SCRSR)
SCRSR is the register used to receive serial data.
The SCIF sets serial data input from the RxD pin in SCRSR in the order received, starting with the
LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to the receive FIFO data register SCFRDR, automatically.
SCRSR cannot be directly read or written to by the CPU.
16.3.2 Receive FIFO Data Register (SCFRDR)
SCFRDR is a 16-stage FIFO register that stores received serial data.
When the SCIF has received one byte of serial data, it transfers the received data from SCRSR to
SCFRDR where it is stored, and completes the receive operation. SCRSR is then enabled for
reception, and consecutive receive operations can be performed until the receive FIFO data
register is full (16 data bytes).
SCFRDR is a read-only register, and cannot be written to by the CPU.
If a read is performed when there is no receive data in the receive FIFO data register, an undefined
value will be returned. When the receive FIFO data register is full of receive data, subsequent
serial data is lost.
The contents of SCFRDR are undefined after a power-on reset or manual reset.
Rev.1.50 Aug. 30, 2006 Page 536 of 860
REJ09B0288-0150