SH7713 Datasheet, PDF (749/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Transmission flowchart
This LSI + memory
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
E-DMAC
Transmit FIFO
EtherC
Ethernet
EtherC/E-DMAC
initialization
Transmit
descriptor and
transmit buffer
setting
Start of transmission
Transmit descriptor read
Transmit data transfer
Transmit descriptor
write-back
Transmit descriptor
read
Transmit data transfer
Frame transmission
Transmit descriptor
write-back
Transmission
completed
[Legend]
EtherC/E-DMAC initialization: Executes a software reset with the SWR bit in EDMR set to 1.
Transmit descriptor and transmit buffer setting: Sets transmit descriptors and transmit buffers, and sets EtherC
and E-DMAC registers, then writes 1 to the TE bit in ECMR
and the TR bit in EDTRR.
Start of transmission: Occurs when 1 is written to the TE bit in ECMR and the TR bit in EDTRR.
Transmit descriptor read: The E-DMAC reads a transmit descriptor.
Transmit data transfer: Writes transmit data to the transmit FIFO by using DMA transfer by the E-DMAC.
Transmit descriptor write-back: The E-DMAC writes 0 to the TACT bit and writes the transmit status to the transmit descriptor.
Figure 19.4 Sample Transmission Flowchart (Single-Frame/Two-Descriptor)
Rev.1.50 Aug. 30, 2006 Page 709 of 860
REJ09B0288-0150