SH7713 Datasheet, PDF (409/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W
6 to 0 
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
• CS3WCR
Bit
31 to
15
Initial
Bit Name Value R/W

All 0 R
14
TRP1
0
R/W
13
TRP0
0
R/W
12

0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Wait Cycles Waiting Completion of Precharge
Specify the number of minimum wait cycles to be inserted
to wait the completion of precharge. The setting for areas 2
and 3 is common.
(1) From starting auto-charge to issuing the ACTV
command
for the same bank
(2) From issuing the PRE/PALL command to issuing the
ACTV command for the same bank
(3) To transiting to power-down mode/deep power-down
mode
(4) From issuing the PALL command at auto-refresh to
issuing the REF command
(5) From issuing the PALL command at self-refresh to
issuing the SELF command
00: 0 cycle
01: 1 cycles
10: 2 cycles
11: 3 cycles
Reserved
This bit is always read as 0. The write value should always
be 0.
Rev.1.50 Aug. 30, 2006 Page 369 of 860
REJ09B0288-0150