SH7713 Datasheet, PDF (255/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 6 Cache
Section 6 Cache
6.1 Features
• Capacity: 16 or 32 kbytes
• Structure: Instructions/data mixed, 4-way set associative
• Locking: Way 2 and way 3 are lockable
• Line size: 16 bytes
• Number of entries: 256 entries/way in 16-kbyte mode to 512 entries/way in 32-kbyte mode
• Write system: Write-back/write-through is selectable for spaces P0, P1, P3, and U0
• Replacement method: Least-recently used (LRU) algorithm
Note: After power-on reset or manual reset, initialized as 16-kbyte mode (256 entries/way).
6.1.1 Cache Structure
The cache mixes instructions and data and uses a 4-way set associative system. It is composed of
four ways (banks), and each of which is divided into an address section and a data section.
Each of the address and data sections is divided into 512 entries. The entry data is called a line.
Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 8 kbytes (16 bytes × 512
entries) in the cache as a whole (4 ways). The cache capacity is 32 kbytes as a whole. Figure 6.1
shows the cache structure.
Address array (ways 0 to 3)
Data array (ways 0 to 3)
LRU
Entry 0 _{V U Tag address}
0 _{LW0 LW1 LW2 LW3}
0
Entry 1
1
1
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Entry 511
24 (1 + 1 + 22) bits
511
128 (32 × 4) bits
LW0 to LW3: Longword data 0 to 3
Figure 6.1 Cache Structure
511
6 bits
Rev.1.50 Aug. 30, 2006 Page 215 of 860
REJ09B0288-0150