SH7713 Datasheet, PDF (694/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.21 TSU Counter Reset Register (TSU_CTRST)
TSU_CTRST clears the transmit and receive frame counters to 0.
Initial
Bit
Bit Name Value R/W Description
31 to 9 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
8
CTRST 0
R/W TSU Counter Reset
When 1 is written to this bit, the values of registers
TXNCR, TXALCR, RXNLCR, and RXALCR, are cleared
to 0. Writing 0 does not affect this bit. These bits are
always read as 0.
7 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
18.3.22 Transmit Frame Counter Register (Normal Transmission Only) (TXNLCR)
TXNLCR is a 32-bit counter indicating the number of frames successfully transmitted in MAC.
When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is
cleared to 0 by a read to this register. This register cannot be written.
Bit
Bit Name Initial Value R/W
31 to 0 NTC031 to All 0
R
NTC000
Description
Transmit Frame Counter Bit
These bits indicate the number of frames
successfully transmitted.
Rev.1.50 Aug. 30, 2006 Page 654 of 860
REJ09B0288-0150