SH7713 Datasheet, PDF (139/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
3.4.2 DSP Data Addressing
Table 3.10 shows the relationship between the double data transfer instructions and single data
transfer instructions.
Table 3.10 Overview of Data Transfer Instructions
Address register
Index register
Addressing
Addressing
Modulo addressing
Data bus
Data length
Bus conflict
Memory
Source register
Destination register
Double Data Transfer Instructions Single Data Transfer Instructions
MOVX.W
MOVY.W
MOVS.W
MOVS.L
Ax: R4, R5,
Ay: R6, R7
As: R2, R3, R4, R5
Ix: R8, Iy: R9
Is: R8
Nop/Inc (+2)/index addition:
post-increment
Nop/Inc (+2, +4)/index addition:
post-increment
—
Dec (–2, –4): pre-decrement
Possible
Not possible
XDB, YDB
LDB
16 bits (word)
16/32 bits (word/longword)
No
Yes
X/Y data memory
Entire memory space
Dx, Dy: A0, A1
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G
Dx: X0/X1
Dy: Y0/Y1
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G
Addressing Mode for Double Data Transfer Instructions: The double data transfer instructions
supports the following three addressing modes.
• Non-update address register addressing
The Ax and Ay registers are address pointers. They are not updated.
• Increment address register addressing
The Ax and Ay registers are address pointers. After a data transfer, they are each incremented
by 2 (post- increment).
• Addition index register addressing
The Ax and Ay registers are address pointers. After a data transfer, the value of the Ix or Iy
register is added to each (post-increment). The double data transfer instructions do not supports
Rev.1.50 Aug. 30, 2006 Page 99 of 860
REJ09B0288-0150