SH7713 Datasheet, PDF (437/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Wait states inserted
by WAIT signal
T1
Tw
Tw
Twx
T2
CKIO
A25 to A0
CSn
RD/WR
Read
RD
D 31 to D0
Write
WEn(BEn)
D31 to D0
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 12.10 Wait State Timing for Normal Space Access (Wait State Insertion by WAIT
Signal)
Rev.1.50 Aug. 30, 2006 Page 397 of 860
REJ09B0288-0150