SH7713 Datasheet, PDF (386/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
30
IWW2
0
29
IWW1
1
28
IWW0
1
R/W Idle Cycles between Write-Read Cycles and Write-Write
R/W ^Cycles
R/W ^{These bits specify the number of idle cycles to be inserted}
after the access to a memory that is connected to the
space. The target access cycles are the write-read cycle
and write-write cycle.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
27
IWRWD2 0
R/W Idle Cycles for Another Space Read-Write
26
IWRWD1 1
25
IWRWD0 1
R/W Specify the number of idle cycles to be inserted after the
R/W ^{access to a memory that is connected to the space. The}
target access cycle is a read-write one in which continuous
accesses switch between different spaces.
000: No idle cycle inserted
001: 1 idle cycles inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
Rev.1.50 Aug. 30, 2006 Page 346 of 860
REJ09B0288-0150